Added test cases

2026-08-22 14:17:27 +02:00 · 2022-02-16 13:27:59 +01:00
parent fb22d7cdc4
commit 271ac28b41
39 changed files with 897 additions and 0 deletions
@@ -0,0 +1,8 @@
+module aldffe( input [0:3] d, input [0:3] ad, input clk, aload, en, output reg [0:3] q );
+	always @( posedge clk, posedge aload)
+		if (aload)
+			q <= ad;
+		else
+			if (en)
+				q <= d;
+endmodule