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Add shregmap -init_msb_first and use in synth_xilinx

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This commit is contained in:
Eddie Hung
2019-03-14 08:10:02 -07:00
parent 79b4a275ce
commit 26ecbc1aee
2 changed files with 16 additions and 4 deletions
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passes/techmap/shregmap.cc
+14 -2
View File
@@ -34,7 +34,7 @@ struct ShregmapOptions
{ {
int minlen, maxlen; int minlen, maxlen;
int keep_before, keep_after; int keep_before, keep_after;
bool zinit, init, params, ffe; bool zinit, init, params, ffe, init_msb_first;
dict<IdString, pair<IdString, IdString>> ffcells; dict<IdString, pair<IdString, IdString>> ffcells;
ShregmapTech *tech; ShregmapTech *tech;
@@ -48,6 +48,7 @@ struct ShregmapOptions
init = false; init = false;
params = false; params = false;
ffe = false; ffe = false;
init_msb_first = false;
tech = nullptr; tech = nullptr;
} }
}; };
@@ -307,6 +308,8 @@ struct ShregmapWorker
initval.push_back(State::S0); initval.push_back(State::S0);
remove_init.insert(bit); remove_init.insert(bit);
} }
if (opts.init_msb_first)
std::reverse(initval.begin(), initval.end());
first_cell->setParam("\\INIT", initval); first_cell->setParam("\\INIT", initval);
} }
@@ -442,9 +445,13 @@ struct ShregmapPass : public Pass {
log("\n"); log("\n");
log(" -init\n"); log(" -init\n");
log(" map initialized registers to the shift reg, add an INIT parameter to\n"); log(" map initialized registers to the shift reg, add an INIT parameter to\n");
log(" generated cells with the initialization value. (first bit to shift out\n"); log(" generated cells with the initialization value. (First bit to shift out\n");
log(" in LSB position)\n"); log(" in LSB position)\n");
log("\n"); log("\n");
log(" -init_msb_first\n");
log(" same as -init, but INIT parameter to have first bit to shift out\n");
log(" in MSB position.\n");
log("\n");
log(" -tech greenpak4\n"); log(" -tech greenpak4\n");
log(" map to greenpak4 shift registers.\n"); log(" map to greenpak4 shift registers.\n");
log("\n"); log("\n");
@@ -515,6 +522,11 @@ struct ShregmapPass : public Pass {
opts.init = true; opts.init = true;
continue; continue;
} }
if (args[argidx] == "-init_msb_first") {
opts.init = true;
opts.init_msb_first = true;
continue;
}
if (args[argidx] == "-params") { if (args[argidx] == "-params") {
opts.params = true; opts.params = true;
continue; continue;
techlibs/xilinx/synth_xilinx.cc
+2 -2
View File
@@ -105,7 +105,7 @@ struct SynthXilinxPass : public Pass
log(" dff2dffe\n"); log(" dff2dffe\n");
log(" opt -full\n"); log(" opt -full\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
log(" shregmap -init -params -enpol any_or_none\n"); log(" shregmap -init_msb_first -params -enpol any_or_none\n");
log(" opt -fast\n"); log(" opt -fast\n");
log("\n"); log("\n");
log(" map_luts:\n"); log(" map_luts:\n");
@@ -225,7 +225,7 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "dff2dffe"); Pass::call(design, "dff2dffe");
Pass::call(design, "opt -full"); Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "shregmap -init_msb_first -params -enpol any_or_none");
Pass::call(design, "opt -fast"); Pass::call(design, "opt -fast");
} }