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memory: fix twines

This commit is contained in:
Emil J. Tywoniak 2026-06-23 16:00:00 +02:00
parent 2255b3f523
commit 25fb9db3d3
2 changed files with 31 additions and 31 deletions
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18
passes/memory/memory_bram.cc
View File

@ -935,7 +935,7 @@ grow_read_ports:;
for (int grid_a = 0; grid_a < acells; grid_a++)
for (int dupidx = 0; dupidx < dup_count; dupidx++)
{
Cell *c = module->addCell(module->uniquify(module->design->twines.add(Twine{stringf("%s.%d.%d.%d", mem.memid.str(), grid_d, grid_a, dupidx)})), module->design->twines.add(Twine{bram.name.str()}));
Cell *c = module->addCell(module->uniquify(module->design->twines.add(std::string{stringf("%s.%d.%d.%d", mem.memid.str(), grid_d, grid_a, dupidx)})), module->design->twines.add(std::string{bram.name.str()}));
log(" Creating %s cell at grid position <%d %d %d>: %s\n", log_id(bram.name), grid_d, grid_a, dupidx, c);
for (auto &vp : variant_params)
@ -964,7 +964,7 @@ grow_read_ports:;
const char *pf = prefix.c_str();
if (pi.clocks && clock_domains.count(pi.clocks))
c->setPort(module->design->twines.add(Twine{stringf("\\CLK%d", (pi.clocks-1) % clocks_max + 1)}), clock_domains.at(pi.clocks).first);
c->setPort(module->design->twines.add(std::string{stringf("\\CLK%d", (pi.clocks-1) % clocks_max + 1)}), clock_domains.at(pi.clocks).first);
if (pi.clkpol > 1 && clock_polarities.count(pi.clkpol))
c->setParam(stringf("\\CLKPOL%d", (pi.clkpol-1) % clkpol_max + 1), clock_polarities.at(pi.clkpol));
if (pi.transp > 1 && read_transp.count(pi.transp))
@ -986,19 +986,19 @@ grow_read_ports:;
}
sig_addr.extend_u0(bram.abits);
c->setPort(module->design->twines.add(Twine{stringf("\\%sADDR", pf)}), sig_addr);
c->setPort(module->design->twines.add(std::string{stringf("\\%sADDR", pf)}), sig_addr);
if (pi.wrmode == 1) {
if (pi.mapped_port == -1)
{
if (pi.enable)
c->setPort(module->design->twines.add(Twine{stringf("\\%sEN", pf)}), Const(State::S0, pi.enable));
c->setPort(module->design->twines.add(std::string{stringf("\\%sEN", pf)}), Const(State::S0, pi.enable));
continue;
}
auto &port = mem.wr_ports[pi.mapped_port];
SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits);
c->setPort(module->design->twines.add(Twine{stringf("\\%sDATA", pf)}), sig_data);
c->setPort(module->design->twines.add(std::string{stringf("\\%sDATA", pf)}), sig_data);
if (pi.enable)
{
@ -1010,21 +1010,21 @@ grow_read_ports:;
if (!addr_ok.empty())
sig_en = module->Mux(NEW_TWINE, SigSpec(0, GetSize(sig_en)), sig_en, addr_ok);
c->setPort(module->design->twines.add(Twine{stringf("\\%sEN", pf)}), sig_en);
c->setPort(module->design->twines.add(std::string{stringf("\\%sEN", pf)}), sig_en);
}
} else {
if (pi.mapped_port == -1)
{
if (pi.enable)
c->setPort(module->design->twines.add(Twine{stringf("\\%sEN", pf)}), State::S0);
c->setPort(module->design->twines.add(std::string{stringf("\\%sEN", pf)}), State::S0);
continue;
}
auto &port = mem.rd_ports[pi.mapped_port];
SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits);
SigSpec bram_dout = module->addWire(NEW_TWINE, bram.dbits);
c->setPort(module->design->twines.add(Twine{stringf("\\%sDATA", pf)}), bram_dout);
c->setPort(module->design->twines.add(std::string{stringf("\\%sDATA", pf)}), bram_dout);
SigSpec addr_ok_q = addr_ok;
if (port.clk_enable && !addr_ok.empty()) {
@ -1039,7 +1039,7 @@ grow_read_ports:;
SigSpec sig_en = port.en;
if (!addr_ok.empty())
sig_en = module->And(NEW_TWINE, sig_en, addr_ok);
c->setPort(module->design->twines.add(Twine{stringf("\\%sEN", pf)}), sig_en);
c->setPort(module->design->twines.add(std::string{stringf("\\%sEN", pf)}), sig_en);
}
}
}

44
passes/memory/memory_libmap.cc
View File

@ -1755,9 +1755,9 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
cell->setParam(stringf("\\PORT_%s_CLK_POL", name), clk_pol);
}
for (auto cell: cells) {
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_CLK", name)}), clk);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_CLK", name)}), clk);
if (pdef.clk_en)
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_CLK_EN", name)}), clk_en);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_CLK_EN", name)}), clk_en);
}
}
@ -1819,7 +1819,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
for (int i = 0; i < hw_wr_wide_log2 && i < hw_rd_wide_log2; i++)
hw_addr[i] = State::S0;
for (auto cell: cells)
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_ADDR", name)}), hw_addr);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_ADDR", name)}), hw_addr);
// Write part.
if (pdef.kind != PortKind::Ar && pdef.kind != PortKind::Sr) {
@ -1850,31 +1850,31 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
hw_wren.append(big_wren[bit.mux_idx][bit.bit]);
}
}
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_DATA", name)}), hw_wdata);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_WR_DATA", name)}), hw_wdata);
if (pdef.wrbe_separate) {
// TODO make some use of it
SigSpec en = mem.module->ReduceOr(NEW_TWINE, hw_wren);
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_EN", name)}), en);
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_BE", name)}), hw_wren);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_WR_EN", name)}), en);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_WR_BE", name)}), hw_wren);
if (cfg.def->width_mode != WidthMode::Single)
cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren));
} else {
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_EN", name)}), hw_wren);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_WR_EN", name)}), hw_wren);
if (cfg.def->byte != 0 && (cfg.def->width_mode != WidthMode::Single || opts.force_params))
cell->setParam(stringf("\\PORT_%s_WR_EN_WIDTH", name), GetSize(hw_wren));
}
}
} else {
for (auto cell: cells) {
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_DATA", name)}), Const(State::Sx, width));
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_WR_DATA", name)}), Const(State::Sx, width));
SigSpec hw_wren = Const(State::S0, width / effective_byte);
if (pdef.wrbe_separate) {
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_EN", name)}), State::S0);
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_BE", name)}), hw_wren);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_WR_EN", name)}), State::S0);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_WR_BE", name)}), hw_wren);
if (cfg.def->width_mode != WidthMode::Single)
cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren));
} else {
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_EN", name)}), hw_wren);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_WR_EN", name)}), hw_wren);
if (cfg.def->byte != 0 && cfg.def->width_mode != WidthMode::Single)
cell->setParam(stringf("\\PORT_%s_WR_EN_WIDTH", name), GetSize(hw_wren));
}
@ -1894,11 +1894,11 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
auto cell = cells[rd];
if (pdef.kind == PortKind::Sr || pdef.kind == PortKind::Srsw) {
if (pdef.rd_en)
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_EN", name)}), rpcfg.rd_en_to_clk_en ? State::S1 : rport.en);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_RD_EN", name)}), rpcfg.rd_en_to_clk_en ? State::S1 : rport.en);
if (pdef.rdarstval != ResetValKind::None)
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_ARST", name)}), rport.arst);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_RD_ARST", name)}), rport.arst);
if (pdef.rdsrstval != ResetValKind::None)
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_SRST", name)}), rport.srst);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_RD_SRST", name)}), rport.srst);
if (pdef.rdinitval == ResetValKind::Any || pdef.rdinitval == ResetValKind::NoUndef) {
Const val = rport.init_value;
if (pdef.rdarstval == ResetValKind::Init && rport.arst != State::S0) {
@ -1949,7 +1949,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
}
}
SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width);
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_DATA", name)}), hw_rdata);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_RD_DATA", name)}), hw_rdata);
SigSpec lhs;
SigSpec rhs;
for (int i = 0; i < GetSize(hw_rdata); i++) {
@ -1965,11 +1965,11 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
for (auto cell: cells) {
if (pdef.kind == PortKind::Sr || pdef.kind == PortKind::Srsw) {
if (pdef.rd_en)
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_EN", name)}), State::S0);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_RD_EN", name)}), State::S0);
if (pdef.rdarstval != ResetValKind::None)
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_ARST", name)}), State::S0);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_RD_ARST", name)}), State::S0);
if (pdef.rdsrstval != ResetValKind::None)
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_SRST", name)}), State::S0);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_RD_SRST", name)}), State::S0);
if (pdef.rdinitval == ResetValKind::Any)
cell->setParam(stringf("\\PORT_%s_RD_INIT_VALUE", name), Const(State::Sx, width));
else if (pdef.rdinitval == ResetValKind::NoUndef)
@ -1984,7 +1984,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), Const(State::S0, width));
}
SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width);
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_DATA", name)}), hw_rdata);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\PORT_%s_RD_DATA", name)}), hw_rdata);
}
}
}
@ -2068,7 +2068,7 @@ void MemMapping::emit(const MemConfig &cfg) {
for (int rp = 0; rp < cfg.repl_port; rp++) {
std::vector<Cell *> cells;
for (int rd = 0; rd < cfg.repl_d; rd++) {
Cell *cell = mem.module->addCell(Twine{stringf("%s.%d.%d", mem.memid.str(), rp, rd)}, mem.module->design->twines.add(Twine{cfg.def->id.str()}));
Cell *cell = mem.module->addCell(mem.module->design->twines.add(std::string{stringf("%s.%d.%d", mem.memid.str(), rp, rd)}), mem.module->design->twines.add(std::string{cfg.def->id.str()}));
if (cfg.def->width_mode == WidthMode::Global || opts.force_params)
cell->setParam(ID::WIDTH, cfg.def->dbits[cfg.base_width_log2]);
if (opts.force_params)
@ -2086,12 +2086,12 @@ void MemMapping::emit(const MemConfig &cfg) {
auto &ccfg = cfg.shared_clocks[i];
if (cdef.anyedge) {
cell->setParam(stringf("\\CLK_%s_POL", cdef.name), ccfg.used ? ccfg.polarity : true);
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\CLK_%s", cdef.name)}), ccfg.used ? ccfg.clk : State::S0);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\CLK_%s", cdef.name)}), ccfg.used ? ccfg.clk : State::S0);
} else {
SigSpec sig = ccfg.used ? ccfg.clk : State::S0;
if (ccfg.used && ccfg.invert)
sig = mem.module->Not(NEW_TWINE, sig);
cell->setPort(mem.module->design->twines.add(Twine{stringf("\\CLK_%s", cdef.name)}), sig);
cell->setPort(mem.module->design->twines.add(std::string{stringf("\\CLK_%s", cdef.name)}), sig);
}
}
if (cfg.def->init == MemoryInitKind::Any || cfg.def->init == MemoryInitKind::NoUndef) {