luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 06:07:26 +02:00
Code Issues Packages Projects Releases Wiki Activity

VHDL only build support

Browse Source
This commit is contained in:
Miodrag Milanovic
2024-06-17 13:29:11 +02:00
parent 54bf9ccf06
commit 25d50bb2af
3 changed files with 144 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Makefile
+10 -1
View File
@@ -20,6 +20,7 @@ ENABLE_VERIFIC := 0
ENABLE_VERIFIC_EDIF := 0
ENABLE_VERIFIC_LIBERTY := 0
DISABLE_VERIFIC_EXTENSIONS := 0
DISABLE_VERIFIC_SYSTEMVERILOG := 0
DISABLE_VERIFIC_VHDL := 0
DISABLE_VERIFIC_HIER_TREE := 0
ENABLE_COVER := 1
@@ -472,7 +473,7 @@ endif
LIBS_VERIFIC =
ifeq ($(ENABLE_VERIFIC),1)
VERIFIC_DIR ?= /usr/local/src/verific_lib
VERIFIC_COMPONENTS ?= verilog database util containers
VERIFIC_COMPONENTS ?= database util containers
ifneq ($(DISABLE_VERIFIC_HIER_TREE),1)
VERIFIC_COMPONENTS += hier_tree
CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT
@@ -481,6 +482,14 @@ ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
VERIFIC_COMPONENTS += hier_tree
endif
endif
ifneq ($(DISABLE_VERIFIC_SYSTEMVERILOG),1)
VERIFIC_COMPONENTS += verilog
CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT
else
ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
VERIFIC_COMPONENTS += verilog
endif
endif
ifneq ($(DISABLE_VERIFIC_VHDL),1)
VERIFIC_COMPONENTS += vhdl
CXXFLAGS += -DVERIFIC_VHDL_SUPPORT