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liberty: better twines

This commit is contained in:
Emil J. Tywoniak 2026-06-23 11:38:48 +02:00
parent e451ceaf5d
commit 2255b3f523
1 changed files with 4 additions and 4 deletions
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8
frontends/liberty/liberty.cc
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@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1; return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
std::string id = RTLIL::escape_id(std::string(expr, id_len)); std::string id = RTLIL::escape_id(std::string(expr, id_len));
TwineRef wire_ref = TwineSearch(&module->design->twines).find(id); TwineRef wire_ref = module->design->twines.find(id);
RTLIL::Wire *w = module->wire(wire_ref); RTLIL::Wire *w = module->wire(wire_ref);
if (!w) if (!w)
log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), module); log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), module);
@ -202,8 +202,8 @@ static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
static std::pair<RTLIL::SigSpec, RTLIL::SigSpec> find_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node) static std::pair<RTLIL::SigSpec, RTLIL::SigSpec> find_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
{ {
TwineRef iq_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(0))); TwineRef iq_ref = module->design->twines.find(RTLIL::escape_id(node->args.at(0)));
TwineRef iqn_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(1))); TwineRef iqn_ref = module->design->twines.find(RTLIL::escape_id(node->args.at(1)));
auto* iq_wire = module->wire(iq_ref); auto* iq_wire = module->wire(iq_ref);
auto* iqn_wire = module->wire(iqn_ref); auto* iqn_wire = module->wire(iqn_ref);
log_assert(iq_wire && iqn_wire); log_assert(iq_wire && iqn_wire);
@ -734,7 +734,7 @@ struct LibertyFrontend : public Frontend {
if (flag_lib && dir->value == "internal") if (flag_lib && dir->value == "internal")
continue; continue;
TwineRef wire_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(0))); TwineRef wire_ref = module->design->twines.find(RTLIL::escape_id(node->args.at(0)));
RTLIL::Wire *wire = module->wire(wire_ref); RTLIL::Wire *wire = module->wire(wire_ref);
log_assert(wire); log_assert(wire);