mirror of https://github.com/YosysHQ/yosys.git
Akash Levy
GitHub
commit
20aec224de
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@ -11,6 +11,7 @@ OBJS += passes/silimate/obs_clean.o
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OBJS += passes/silimate/segv.o
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OBJS += passes/silimate/reg_rename.o
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OBJS += passes/silimate/infer_ce.o
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OBJS += passes/silimate/report_fanout.o
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OBJS += passes/silimate/splitfanout.o
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OBJS += passes/silimate/splitlarge.o
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OBJS += passes/silimate/splitnetlist.o
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@ -0,0 +1,270 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2025 Silimate Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <memory>
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Worker that counts fanout for each driver (input ports and cell output ports)
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// and reports any that exceed a user-specified limit.
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struct ReportFanoutWorker
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{
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Module *module;
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SigMap sigmap;
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// Maps each driven SigBit to its fanout count
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dict<SigBit, int> bit_fanout;
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// Maps each driven SigBit back to its driver:
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// - For input ports: driver_port[bit] = (wire_name, IdString())
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// - For cell output ports: driver_port[bit] = (cell_name, port_name)
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dict<SigBit, pair<IdString, IdString>> bit_driver;
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// SigBits that are clock or reset signals (driven into CLK/RST/ARST ports)
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pool<SigBit> clk_rst_bits;
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ReportFanoutWorker(Module *module, bool skip_clk_rst) : module(module), sigmap(module)
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{
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// Record drivers from input ports
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// Every bit of an input port wire is a driver into the module
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for (auto wire : module->wires()) {
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if (!wire->port_input) continue;
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(sig); i++) {
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SigBit bit = sig[i];
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bit_driver[bit] = {wire->name, IdString()};
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}
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}
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// Record drivers from cell output ports
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections()) {
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if (!cell->output(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit = sigmap(conn.second[i]);
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bit_driver[bit] = {cell->name, conn.first};
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}
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}
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}
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// Identify clock and reset signals by looking at FF cell ports,
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// then trace backwards through driver cells to mark the original
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// source bits (handles intermediate cells like $reduce_or inserted
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// by proc_dff between input ports and FF ARST/CLK).
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if (skip_clk_rst) {
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for (auto cell : module->cells()) {
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for (auto port_id : {ID(CLK), ID(C)}) {
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if (cell->hasPort(port_id)) {
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SigSpec sig = sigmap(cell->getPort(port_id));
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for (auto bit : sig)
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clk_rst_bits.insert(bit);
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}
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}
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for (auto port_id : {ID(RST), ID(ARST), ID(SRST), ID(R), ID(S)}) {
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if (cell->hasPort(port_id)) {
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SigSpec sig = sigmap(cell->getPort(port_id));
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for (auto bit : sig)
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clk_rst_bits.insert(bit);
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}
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}
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}
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// Build a map from each driven bit to the cell that drives it
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dict<SigBit, Cell*> bit_to_cell;
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections()) {
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if (!cell->output(conn.first)) continue;
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for (auto bit : sigmap(conn.second))
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bit_to_cell[bit] = cell;
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}
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}
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// Iteratively trace backwards: if a clk/rst bit is driven by a
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// cell, mark all of that cell's input bits as clk/rst too.
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bool changed = true;
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while (changed) {
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changed = false;
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pool<SigBit> new_bits;
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for (auto bit : clk_rst_bits) {
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auto it = bit_to_cell.find(bit);
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if (it == bit_to_cell.end()) continue;
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Cell *drv_cell = it->second;
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for (auto &conn : drv_cell->connections()) {
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if (!drv_cell->input(conn.first)) continue;
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for (auto inp_bit : sigmap(conn.second)) {
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if (!clk_rst_bits.count(inp_bit))
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new_bits.insert(inp_bit);
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}
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}
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}
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if (!new_bits.empty()) {
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changed = true;
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for (auto bit : new_bits)
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clk_rst_bits.insert(bit);
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}
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}
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}
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// Count fanout: each cell input pin connection is one fanout
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections()) {
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if (!cell->input(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit = sigmap(conn.second[i]);
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if (bit_driver.count(bit))
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bit_fanout[bit]++;
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}
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}
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}
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// Count fanout: each output port connection is one fanout
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for (auto wire : module->wires()) {
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if (!wire->port_output) continue;
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(sig); i++) {
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SigBit bit = sig[i];
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if (bit_driver.count(bit))
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bit_fanout[bit]++;
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}
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}
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}
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// Report all drivers whose total fanout exceeds the limit.
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// Aggregates per-bit fanout to the (driver, port) level.
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// If f is non-null, also writes the same lines to that file.
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void report(int limit, FILE *f = nullptr)
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{
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// Aggregate fanout per driver (identified by driver_name + port_name),
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// skipping bits identified as clock or reset signals.
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dict<pair<IdString, IdString>, int> driver_fanout;
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for (auto &entry : bit_fanout) {
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SigBit bit = entry.first;
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if (clk_rst_bits.count(bit))
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continue;
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int count = entry.second;
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auto &drv = bit_driver.at(bit);
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driver_fanout[drv] += count;
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}
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// Report any driver exceeding the limit
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for (auto &entry : driver_fanout) {
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int fanout = entry.second;
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if (fanout <= limit) continue;
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IdString driver_name = entry.first.first;
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IdString port_name = entry.first.second;
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if (port_name == IdString()) {
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// Driver is an input port
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log_warning("(%s, %s) = %d\n",
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log_id(module), log_id(driver_name), fanout);
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if (f)
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fprintf(f, "(%s, %s) = %d\n",
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log_id(module), log_id(driver_name), fanout);
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} else {
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// Driver is a cell output port
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log_warning("(%s, %s, %s) = %d\n",
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log_id(module), log_id(driver_name), log_id(port_name), fanout);
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if (f)
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fprintf(f, "(%s, %s, %s) = %d\n",
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log_id(module), log_id(driver_name), log_id(port_name), fanout);
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}
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}
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}
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};
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struct ReportFanoutPass : public Pass {
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ReportFanoutPass() : Pass("report_fanout", "report nets with fanout exceeding a limit") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" report_fanout -limit <n> [-file <filename>] [-include_clk_rst] [selection]\n");
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log("\n");
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log("This command reports all input ports and cell output ports whose fanout\n");
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log("exceeds the specified limit. Results are printed as log_warning messages.\n");
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log("\n");
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log("By default, nets driving clock or reset ports (CLK, C, RST, ARST, SRST,\n");
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log("R, S) on flip-flops are excluded from the report.\n");
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log("\n");
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log(" -limit n\n");
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log(" fanout threshold. Nets with fanout > n are reported.\n");
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log("\n");
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log(" -file filename\n");
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log(" also write the report to the specified file.\n");
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log("\n");
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log(" -include_clk_rst\n");
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log(" include clock and reset nets in the report.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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int limit = -1;
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std::string filename;
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bool include_clk_rst = false;
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log_header(design, "Executing REPORT_FANOUT pass (reporting nets with high fanout).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-limit" && argidx + 1 < args.size()) {
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try {
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limit = std::stoi(args[++argidx]);
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} catch (...) {
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log_cmd_error("Invalid value for -limit: '%s'. Expected an integer.\n", args[argidx].c_str());
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}
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continue;
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}
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if (args[argidx] == "-file" && argidx + 1 < args.size()) {
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filename = args[++argidx];
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continue;
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}
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if (args[argidx] == "-include_clk_rst") {
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include_clk_rst = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (limit < 0)
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log_cmd_error("Missing required -limit option (must be a non-negative integer).\n");
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// Open output file if requested
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std::unique_ptr<FILE, decltype(&fclose)> f(nullptr, &fclose);
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if (!filename.empty()) {
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f.reset(fopen(filename.c_str(), "w"));
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if (!f)
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log_cmd_error("Cannot open file '%s' for writing.\n", filename.c_str());
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}
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bool skip_clk_rst = !include_clk_rst;
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for (auto module : design->selected_modules())
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{
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log("Analyzing fanout for module %s...\n", log_id(module));
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ReportFanoutWorker worker(module, skip_clk_rst);
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worker.report(limit, f.get());
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}
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}
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} ReportFanoutPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,252 @@
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# Test 1: Input port with high fanout is reported
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# Input 'a' fans out to 5 output ports, limit is 3 => should warn for 'a'
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# Input 'b' fans out to 2 output ports (<= 3) => no warn for 'b'
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log -header "Input port fanout exceeds limit"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire x1,
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output wire x2
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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assign x1 = b;
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assign x2 = b;
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endmodule
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EOF
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proc -noopt
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opt_clean -purge
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# 'a' has fanout 5 (> 3), 'b' has fanout 2 (<= 3)
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# Expect exactly one warning for input port 'a'
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logger -expect warning "\(top, a\) = 5" 1
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report_fanout -limit 3
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design -reset
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log -pop
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# Test 2: Cell output port with high fanout is reported
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# AND gate output fans out to 5 output ports, limit is 2 => should warn
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log -header "Cell output port fanout exceeds limit"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5
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);
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wire and_out = a & b;
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assign w1 = and_out;
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assign w2 = and_out;
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assign w3 = and_out;
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assign w4 = and_out;
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assign w5 = and_out;
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endmodule
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EOF
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proc -noopt
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opt_clean -purge
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# The $and cell's Y port fans out to 5 (> 2)
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# Input ports a and b each fan out to 1 cell input (<= 2), no warn for them
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logger -expect warning "\(top, .*, Y\) = 5" 1
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report_fanout -limit 2
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design -reset
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log -pop
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# Test 3: No warnings when all fanouts are within the limit
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log -header "No fanout exceeds limit"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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output wire w1,
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output wire w2
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);
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wire and_out = a & b;
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assign w1 = and_out;
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assign w2 = and_out;
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endmodule
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EOF
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proc -noopt
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opt_clean -purge
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# All fanouts <= 10, so no warnings expected
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logger -expect-no-warnings
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report_fanout -limit 10
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design -reset
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log -pop
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# Test 4: Multiple cell output ports reported in the same module
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# Two cells each have fanout of 3, limit is 1 => two warnings
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log -header "Multiple cells with high fanout"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire x1,
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output wire x2,
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output wire x3
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);
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wire and_out = a & b;
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wire or_out = a | c;
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assign w1 = and_out;
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assign w2 = and_out;
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assign w3 = and_out;
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assign x1 = or_out;
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assign x2 = or_out;
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assign x3 = or_out;
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endmodule
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EOF
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proc -noopt
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opt_clean -purge
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# Both cells' Y ports fan out to 3 (> 1). Input 'a' fans out to 2 cell inputs (> 1).
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# Expect 3 warnings total.
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logger -expect warning "\(top, .*, Y\) = 3" 2
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logger -expect warning "\(top, a\) = 2" 1
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report_fanout -limit 1
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design -reset
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log -pop
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# Test 5: Mixed - input port AND cell output both exceed limit
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log -header "Input port and cell output both exceed limit"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire y1,
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output wire y2,
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output wire y3
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);
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wire not_out = !a;
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign y1 = not_out;
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assign y2 = not_out;
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assign y3 = not_out;
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endmodule
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EOF
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proc -noopt
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opt_clean -purge
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# 'a' fans out to 3 output ports + 1 cell input = 4 total (> 2)
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# $logic_not Y fans out to 3 (> 2)
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logger -expect warning "\(top, a\) = 4" 1
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logger -expect warning "\(top, .*, Y\) = 3" 1
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report_fanout -limit 2
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design -reset
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log -pop
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||||
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# Test 6: Clock and reset ports are excluded by default
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log -header "Clock and reset exclusion"
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log -push
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design -reset
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||||
read_verilog <<EOF
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module top (
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input wire clk,
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input wire rst,
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input wire [3:0] d,
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||||
output reg [3:0] q
|
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);
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// Four separate always blocks to create four independent $adff cells
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always @(posedge clk or posedge rst) begin
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if (rst) q[0] <= 1'b0; else q[0] <= d[0];
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end
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always @(posedge clk or posedge rst) begin
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if (rst) q[1] <= 1'b0; else q[1] <= d[1];
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end
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||||
always @(posedge clk or posedge rst) begin
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if (rst) q[2] <= 1'b0; else q[2] <= d[2];
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end
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||||
always @(posedge clk or posedge rst) begin
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if (rst) q[3] <= 1'b0; else q[3] <= d[3];
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||||
end
|
||||
endmodule
|
||||
EOF
|
||||
proc -noopt
|
||||
opt_clean -purge
|
||||
|
||||
# 'clk' and 'rst' each fan out to 4 FF cells but are excluded by default
|
||||
# 'd' is 4 bits wide, each bit fans out to 1 FF (aggregated = 4), not excluded
|
||||
logger -expect warning "\(top, d\) = 4" 1
|
||||
report_fanout -limit 3
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
# Test 7: -include_clk_rst makes clock/reset nets reportable
|
||||
log -header "Clock and reset included with -include_clk_rst"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [3:0] d,
|
||||
output reg [3:0] q
|
||||
);
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) q[0] <= 1'b0; else q[0] <= d[0];
|
||||
end
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) q[1] <= 1'b0; else q[1] <= d[1];
|
||||
end
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) q[2] <= 1'b0; else q[2] <= d[2];
|
||||
end
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) q[3] <= 1'b0; else q[3] <= d[3];
|
||||
end
|
||||
endmodule
|
||||
EOF
|
||||
proc -noopt
|
||||
opt_clean -purge
|
||||
|
||||
# With -include_clk_rst, clk and rst (fanout 4 each) should be reported
|
||||
logger -expect warning "\(top, d\) = 4" 1
|
||||
logger -expect warning "\(top, clk\) = 4" 1
|
||||
logger -expect warning "\(top, rst\) = 4" 1
|
||||
report_fanout -limit 3 -include_clk_rst
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Reference in New Issue