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https://github.com/YosysHQ/yosys.git
synced 2026-08-22 14:17:27 +02:00
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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@@ -296,7 +296,7 @@ namespace
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SigSet<std::pair<std::string, int>> sig2port;
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// create new cell
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RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
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RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
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// create cell ports
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for (auto &it : needle->wires_) {
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@@ -161,7 +161,7 @@ struct TechmapWorker
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for (auto &it : tpl->cells_)
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if (it.first == "\\_TECHMAP_REPLACE_") {
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orig_cell_name = cell->name;
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module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
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module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name);
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break;
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}
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