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CODEOWNERS: add myself for read_verilog and AST

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Emil J. Tywoniak 2025-09-15 16:48:56 +02:00
parent 7d82d80a95
commit 1c422fcb6e
1 changed files with 2 additions and 2 deletions
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@ -30,8 +30,8 @@ docs/source/using_yosys/synthesis/abc.rst @KrystalDelusion @Ravenslofty
# These still override previous lines, so be careful not to # These still override previous lines, so be careful not to
# accidentally disable any of the above rules. # accidentally disable any of the above rules.
frontends/verilog/ @zachjs frontends/verilog/ @widlarizer
frontends/ast/ @zachjs frontends/ast/ @widlarizer
techlibs/intel_alm/ @Ravenslofty techlibs/intel_alm/ @Ravenslofty
techlibs/gowin/ @pepijndevos techlibs/gowin/ @pepijndevos