mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'YosysHQ:main' into main
This commit is contained in:
commit
1a966c4459
2
Makefile
2
Makefile
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@ -177,7 +177,7 @@ ifeq ($(OS), Haiku)
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CXXFLAGS += -D_DEFAULT_SOURCE
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endif
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YOSYS_VER := 0.59+30
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YOSYS_VER := 0.59+44
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YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
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YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
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YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
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@ -276,7 +276,7 @@ RTLIL::IdString new_id_suffix(std::string_view file, int line, std::string_view
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#define NEW_ID \
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YOSYS_NAMESPACE_PREFIX RTLIL::IdString::new_autoidx_with_prefix([](std::string_view func) -> const std::string * { \
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static const std::string *prefix = create_id_prefix(__FILE__, __LINE__, func); \
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static const std::string *prefix = YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func); \
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return prefix; \
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}(__FUNCTION__))
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#define NEW_ID_SUFFIX(suffix) \
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@ -199,8 +199,15 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
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}
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SigSpec sig_y = sig_d, sig_undef;
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if (!ignore_self_reset && ce.eval(sig_y, sig_undef))
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is_self_resetting = true;
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if (!ignore_self_reset) {
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if (cellport.first->type == ID($adff)) {
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SigSpec sig_arst = assign_map(cellport.first->getPort(ID::ARST));
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if (ce.eval(sig_arst, sig_undef))
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is_self_resetting = true;
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}
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else if (ce.eval(sig_y, sig_undef))
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is_self_resetting = true;
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}
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}
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if (has_fsm_encoding_attr)
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@ -0,0 +1,121 @@
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read_verilog << EOT
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module non_self_rs_fsm (
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input wire clk,
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input wire reset,
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output wire s1
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);
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localparam [7:0] RST = 8'b10010010;
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localparam [7:0] S1 = 8'b01001000;
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localparam [7:0] S2 = 8'b11000111;
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reg [7:0] current_state, next_state;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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current_state <= RST;
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end else begin
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current_state <= next_state;
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end
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end
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always @(*) begin
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next_state = current_state;
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case (current_state)
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RST: next_state = S1;
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S1: next_state = S2;
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S2: next_state = S1;
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default: next_state = RST;
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endcase
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end
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assign s1 = next_state == S1;
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endmodule
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module semi_self_rs_fsm (
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input wire clk,
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input wire test,
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output wire s1
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);
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localparam [7:0] RST = 8'b10010010;
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localparam [7:0] S1 = 8'b01001000;
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localparam [7:0] S2 = 8'b11000111;
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reg [7:0] current_state, next_state;
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reg [1:0] reset_test;
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wire reset = (test || (reset_test == 2));
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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current_state <= RST;
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reset_test <= 0;
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end else begin
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current_state <= next_state;
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if (current_state == S2)
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reset_test = reset_test + 1;
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end
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end
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always @(*) begin
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next_state = current_state;
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case (current_state)
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RST: next_state = S1;
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S2: next_state = S1;
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S1: next_state = S2;
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default: next_state = RST;
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endcase
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end
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assign s1 = next_state == S1;
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endmodule
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module self_rs_fsm (
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input wire clk,
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output wire s1
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);
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localparam [7:0] RST = 8'b10010010;
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localparam [7:0] S1 = 8'b01001000;
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localparam [7:0] S2 = 8'b11000111;
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reg [7:0] next_state;
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wire reset = next_state == S1;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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next_state <= RST;
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end else begin
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case (next_state)
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RST: next_state = S1;
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S1: next_state = S2;
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S2: next_state = S1;
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default: next_state = RST;
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endcase
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end
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end
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assign s1 = next_state == S1;
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endmodule
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EOT
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proc
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opt_expr
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opt_clean
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check
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opt -nodffe -nosdff
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fsm_detect
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fsm_extract
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cd non_self_rs_fsm
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select -assert-count 1 t:$fsm
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cd semi_self_rs_fsm
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select -assert-count 1 t:$fsm
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cd self_rs_fsm
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select -assert-none t:$fsm
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