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Fix.

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nella
2026-06-24 11:11:19 +02:00
parent a3b8609c84
commit 1186e5af61
1 changed files with 0 additions and 13 deletions
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tests/various/check_nolatches.ys
-13
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@@ -21,17 +21,6 @@ check -nolatches -assert
design -reset design -reset
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
proc
logger -expect error "Found 1 problems in" 1
check -nolatches -assert
design -reset
read_verilog <<EOT read_verilog <<EOT
module top(input g, d, output reg q, output y); module top(input g, d, output reg q, output y);
always @* if (g) q = d; always @* if (g) q = d;
@@ -40,7 +29,5 @@ assign y = u;
endmodule endmodule
EOT EOT
proc proc
logger -expect warning "is a latch of type" 1
logger -expect warning "used but has no driver" 0
logger -expect error "Found 1 problems in" 1 logger -expect error "Found 1 problems in" 1
check -latchonly -assert check -latchonly -assert