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write_verilog: emit initial $display correctly.

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Catherine
2024-01-11 13:13:04 +01:00
committed by Dag Lem
parent 0486f61a35
commit 1159e48721
3 changed files with 18 additions and 12 deletions
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frontends/ast/genrtlil.cc
+1 -1
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@@ -718,7 +718,7 @@ struct AST_INTERNAL::ProcessGenerator
}
}
cell->parameters[ID::TRG_WIDTH] = triggers.size();
cell->parameters[ID::TRG_ENABLE] = !triggers.empty();
cell->parameters[ID::TRG_ENABLE] = (always->type == AST_INITIAL) || !triggers.empty();
cell->parameters[ID::TRG_POLARITY] = polarity;
cell->parameters[ID::PRIORITY] = --last_print_priority;
cell->setPort(ID::TRG, triggers);