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Refactoring: Renamed RTLIL::Design::modules to modules_

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Clifford Wolf
2014-07-27 11:18:30 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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passes/techmap/iopadmap.cc
+1 -1
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@@ -111,7 +111,7 @@ struct IopadmapPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &it : design->modules)
for (auto &it : design->modules_)
{
RTLIL::Module *module = it.second;