Added "yosys -D" feature

passes/fsm/fsm.cc

@@ -76,7 +76,7 @@ struct FsmPass : public Pass {
 		std::string encfile_opt;
 		std::string encoding_opt;
 
-		log_header("Executing FSM pass (extract and optimize FSM).\n");
+		log_header(design, "Executing FSM pass (extract and optimize FSM).\n");
 		log_push();
 
 		size_t argidx;

passes/fsm/fsm_detect.cc

@@ -154,7 +154,7 @@ struct FsmDetectPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_DETECT pass (finding FSMs in design).\n");
+		log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
 		extra_args(args, 1, design);
 
 		CellTypes ct;

passes/fsm/fsm_expand.cc

@@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
+		log_header(design, "Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
 		extra_args(args, 1, design);
 
 		for (auto &mod_it : design->modules_) {

passes/fsm/fsm_export.cc

@@ -152,7 +152,7 @@ struct FsmExportPass : public Pass {
 		bool flag_origenc = false;
 		size_t argidx;
 
-		log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
+		log_header(design, "Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
 
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			arg = args[argidx];

passes/fsm/fsm_extract.cc

@@ -416,7 +416,7 @@ struct FsmExtractPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_EXTRACT pass (extracting FSM from design).\n");
+		log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
 		extra_args(args, 1, design);
 
 		CellTypes ct;

passes/fsm/fsm_info.cc

@@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
+		log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
 		extra_args(args, 1, design);
 
 		for (auto &mod_it : design->modules_)

passes/fsm/fsm_map.cc

@@ -335,7 +335,7 @@ struct FsmMapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
+		log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
 		extra_args(args, 1, design);
 
 		for (auto &mod_it : design->modules_) {

passes/fsm/fsm_opt.cc

@@ -336,7 +336,7 @@ struct FsmOptPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n");
+		log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
 		extra_args(args, 1, design);
 
 		for (auto &mod_it : design->modules_) {

passes/fsm/fsm_recode.cc

@@ -157,7 +157,7 @@ struct FsmRecodePass : public Pass {
 		FILE *encfile = NULL;
 		std::string default_encoding;
 
-		log_header("Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");
+		log_header(design, "Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];