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Merge pull request #109 from Silimate/clkgate_attr 

Added is_clock_gated attr to flops created via clockgate.cc pass
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Akash Levy 2026-02-20 17:02:02 -08:00 committed by GitHub
parent c47dd20140 8f5b8cb46c
commit 0b46d8b201
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GPG Key ID: B5690EEEBB952194
2 changed files with 3 additions and 1 deletions
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1
kernel/constids.inc
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@ -909,6 +909,7 @@ X(interface_type)
X(interfaces_replaced_in_module) X(interfaces_replaced_in_module)
X(invertible_pin) X(invertible_pin)
X(iopad_external_pin) X(iopad_external_pin)
X(is_clock_gated)
X(is_inferred) X(is_inferred)
X(is_interface) X(is_interface)
X(it) X(it)

3
passes/techmap/clockgate.cc
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@ -428,7 +428,8 @@ struct ClockgatePass : public Pass {
ff.sig_clk = (*it).second.new_net; ff.sig_clk = (*it).second.new_net;
// Rebuild the flop // Rebuild the flop
(void)ff.emit(); Cell *new_ff = ff.emit();
new_ff->set_bool_attribute(ID::is_clock_gated);
gated_flop_count++; gated_flop_count++;
} }