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synth_xilinx: remove classic ABC mapping

This commit is contained in:
Lofty 2026-08-04 13:53:47 +01:00 committed by Lofty
parent 44bab117d7
commit 086cd8e685
5 changed files with 39 additions and 76 deletions
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72
techlibs/xilinx/synth_xilinx.cc
View File

@ -127,14 +127,7 @@ struct SynthXilinxPass : public ScriptPass
log(" flatten design before synthesis\n"); log(" flatten design before synthesis\n");
log("\n"); log("\n");
log(" -dff\n"); log(" -dff\n");
log(" run 'abc'/'abc9' with -dff option\n"); log(" run 'abc9' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
log(" implies -dff.\n");
log("\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n"); log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
@ -143,8 +136,8 @@ struct SynthXilinxPass : public ScriptPass
} }
std::string top_opt, edif_file, blif_file, json_file, family; std::string top_opt, edif_file, blif_file, json_file, family;
bool flatten, retime, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram; bool flatten, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
bool abc9, dff; bool dff;
bool flatten_before_abc; bool flatten_before_abc;
int widemux; int widemux;
int lut_size; int lut_size;
@ -157,7 +150,6 @@ struct SynthXilinxPass : public ScriptPass
blif_file.clear(); blif_file.clear();
family = "xc7"; family = "xc7";
flatten = false; flatten = false;
retime = false;
ise = false; ise = false;
noiopad = false; noiopad = false;
noclkbuf = false; noclkbuf = false;
@ -169,7 +161,6 @@ struct SynthXilinxPass : public ScriptPass
nowidelut = false; nowidelut = false;
nodsp = false; nodsp = false;
uram = false; uram = false;
abc9 = false;
dff = false; dff = false;
flatten_before_abc = false; flatten_before_abc = false;
widemux = 0; widemux = 0;
@ -218,7 +209,7 @@ struct SynthXilinxPass : public ScriptPass
} }
if (args[argidx] == "-retime") { if (args[argidx] == "-retime") {
dff = true; dff = true;
retime = true; // retiming not supported by ABC9
continue; continue;
} }
if (args[argidx] == "-nocarry") { if (args[argidx] == "-nocarry") {
@ -265,7 +256,7 @@ struct SynthXilinxPass : public ScriptPass
continue; continue;
} }
if (args[argidx] == "-abc9") { if (args[argidx] == "-abc9") {
abc9 = true; // removed: abc9 enabled by default
continue; continue;
} }
if (args[argidx] == "-nodsp") { if (args[argidx] == "-nodsp") {
@ -326,9 +317,6 @@ struct SynthXilinxPass : public ScriptPass
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
if (abc9 && retime)
log_cmd_error("-retime option not currently compatible with -abc9!\n");
log_header(design, "Executing SYNTH_XILINX pass.\n"); log_header(design, "Executing SYNTH_XILINX pass.\n");
log_push(); log_push();
@ -630,11 +618,9 @@ struct SynthXilinxPass : public ScriptPass
run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01", "(for xc6v, xc7, xcu, xcup)"); run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01", "(for xc6v, xc7, xcu, xcup)");
else else
run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_DFFSRE_?PPP_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01 -cell $_DLATCHSR_?PP_ 01", "(for xc5v and older)"); run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_DFFSRE_?PPP_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01 -cell $_DLATCHSR_?PP_ 01", "(for xc5v and older)");
if (abc9 || help_mode) { if (dff || help_mode)
if (dff || help_mode) run("zinit -all w:* t:$_SDFFE_*", "('-dff' only)");
run("zinit -all w:* t:$_SDFFE_*", "('-dff' only)"); run("techmap -map +/xilinx/ff_map.v");
run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)");
}
} }
if (check_label("map_luts")) { if (check_label("map_luts")) {
@ -644,13 +630,8 @@ struct SynthXilinxPass : public ScriptPass
run("flatten"); run("flatten");
} }
if (help_mode) if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')"); run("abc9 -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff')");
else if (abc9) { else {
if (lut_size != 6)
log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n");
if (family != "xc7")
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v"); run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
std::string abc9_opts; std::string abc9_opts;
std::string k = "synth_xilinx.abc9.W"; std::string k = "synth_xilinx.abc9.W";
@ -660,37 +641,20 @@ struct SynthXilinxPass : public ScriptPass
k = stringf("synth_xilinx.abc9.%s.W", family); k = stringf("synth_xilinx.abc9.%s.W", family);
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W"))); abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")));
} }
if (nowidelut) if (lut_size != 6) {
abc9_opts += stringf(" -maxlut %d", lut_size); abc9_opts += " -lut " + lut_size_s;
if (!nowidelut)
abc9_opts += ":" + std::to_string(widelut_size);
} else {
if (nowidelut)
abc9_opts += stringf(" -maxlut %d", lut_size);
}
if (dff) if (dff)
abc9_opts += " -dff"; abc9_opts += " -dff";
run("abc9" + abc9_opts); run("abc9" + abc9_opts);
} }
else {
std::string abc_opts;
if (lut_size != 6) {
if (nowidelut)
abc_opts += " -lut " + lut_size_s;
else
abc_opts += " -lut " + lut_size_s + ":" + std::to_string(widelut_size);
} else {
if (nowidelut)
abc_opts += " -luts 2:2,3,6:5";
else if (widelut_size == 8)
abc_opts += " -luts 2:2,3,6:5,10,20";
else
abc_opts += " -luts 2:2,3,6:5,10,20,40";
}
if (dff)
abc_opts += " -dff";
if (retime)
abc_opts += " -D 1";
run("abc" + abc_opts);
}
run("clean"); run("clean");
if (help_mode || !abc9)
run("techmap -map +/xilinx/ff_map.v", "(only if not '-abc9')");
// This shregmap call infers fixed length shift registers after abc // This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming // has performed any necessary retiming
if (!nosrl || help_mode) if (!nosrl || help_mode)

12
tests/arch/xilinx/add_sub.ys
View File

@ -6,18 +6,18 @@ design -save orig
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
stat select -assert-count 1 t:INV
select -assert-count 8 t:LUT2 select -assert-count 7 t:LUT2
select -assert-count 2 t:CARRY4 select -assert-count 2 t:CARRY4
select -assert-none t:LUT2 t:CARRY4 %% t:* %D select -assert-none t:INV t:LUT2 t:CARRY4 %% t:* %D
design -load orig design -load orig
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
stat select -assert-count 4 t:INV
select -assert-count 8 t:LUT2 select -assert-count 4 t:LUT2
select -assert-count 6 t:MUXCY select -assert-count 6 t:MUXCY
select -assert-count 8 t:XORCY select -assert-count 8 t:XORCY
select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D select -assert-none t:INV t:LUT2 t:MUXCY t:XORCY %% t:* %D

7
tests/arch/xilinx/fsm.ys
View File

@ -30,8 +30,7 @@ cd fsm # Constrain all select calls below inside the top module
stat stat
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE select -assert-count 6 t:FDRE
select -assert-count 1 t:LUT1 select -assert-max 6 t:LUT3
select -assert-max 1 t:LUT3 select -assert-max 6 t:LUT4
select -assert-max 8 t:LUT4
select -assert-count 5 t:MUXF5 select -assert-count 5 t:MUXF5
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:MUXF5 %% t:* %D

4
tests/arch/xilinx/logic.ys
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@ -5,7 +5,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:INV select -assert-count 4 t:INV
select -assert-count 6 t:LUT2 select -assert-count 3 t:LUT2
select -assert-count 2 t:LUT4 select -assert-count 2 t:LUT4
select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D

20
tests/arch/xilinx/mux_lut4.ys
View File

@ -20,7 +20,6 @@ cd mux4 # Constrain all select calls below inside the top module
select -assert-count 4 t:LUT1 select -assert-count 4 t:LUT1
select -assert-count 2 t:MUXF5 select -assert-count 2 t:MUXF5
select -assert-count 1 t:MUXF6 select -assert-count 1 t:MUXF6
select -assert-none t:LUT1 t:MUXF5 t:MUXF6 %% t:* %D select -assert-none t:LUT1 t:MUXF5 t:MUXF6 %% t:* %D
@ -30,13 +29,11 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-max 5 t:LUT1 select -assert-max 1 t:LUT3
select -assert-max 3 t:LUT3 select -assert-max 5 t:LUT4
select -assert-max 3 t:LUT4 select -assert-max 1 t:MUXF5
select -assert-max 3 t:MUXF5
select -assert-count 1 t:MUXF6
select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D select -assert-none t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
design -load read design -load read
@ -45,8 +42,11 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-max 32 t:LUT* select -assert-max 14 t:LUT3
select -assert-max 20 t:LUT4
select -assert-max 16 t:MUXF5
select -assert-max 8 t:MUXF6 select -assert-max 8 t:MUXF6
select -assert-max 4 t:MUXF7 select -assert-max 3 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 %% t:* %D select -assert-none t:LUT3 t:LUT4 t:MUXF5 t:MUXF6 t:MUXF7 t:MUXF8 %% t:* %D