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clk2fflogic: Consistently treat async control signals as negative hold.

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This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
This commit is contained in:
Marcelina Kościelnicka
2020-07-09 18:12:47 +02:00
parent e9c2c1b717
commit 03e28f7ab4
8 changed files with 81 additions and 87 deletions
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tests/techmap/dfflegalize_sr.ys
+6 -6
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@@ -9,12 +9,12 @@ endmodule
EOT
design -save orig
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
# Convert everything to SRs.