luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Extend testcase

This commit is contained in:
Eddie Hung 2019-02-06 14:02:11 -08:00
parent a9674bd2ec
commit 03cf1532a7
1 changed files with 34 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
tests/simple/dff_init.v
View File

@ -1,6 +1,5 @@
module dff_test(n1, n1_inv, clk); module dff0_test(n1, n1_inv, clk);
input clk; input clk;
(* init = 32'd0 *)
output n1; output n1;
reg n1 = 32'd0; reg n1 = 32'd0;
output n1_inv; output n1_inv;
@ -8,3 +7,36 @@ module dff_test(n1, n1_inv, clk);
n1 <= n1_inv; n1 <= n1_inv;
assign n1_inv = ~n1; assign n1_inv = ~n1;
endmodule endmodule
module dff1_test(n1, n1_inv, clk);
input clk;
(* init = 32'd1 *)
output n1;
reg n1 = 32'd1;
output n1_inv;
always @(posedge clk)
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
module dff0a_test(n1, n1_inv, clk);
input clk;
(* init = 32'd0 *) // Must be consistent with reg initialiser below
output n1;
reg n1 = 32'd0;
output n1_inv;
always @(posedge clk)
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
module dff1a_test(n1, n1_inv, clk);
input clk;
(* init = 32'd1 *) // Must be consistent with reg initialiser below
output n1;
reg n1 = 32'd1;
output n1_inv;
always @(posedge clk)
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule