Replace "ILANG" with "RTLIL" everywhere.

The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.

passes/hierarchy/hierarchy.cc

@@ -224,7 +224,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 				{
 					{".v", "verilog"},
 					{".sv", "verilog -sv"},
-					{".il", "ilang"}
+					{".il", "rtlil"}
 				};
 
 				for (auto &ext : extensions_list)