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fc6433bbae52cfda8d012b9dc2c522fd625b3134
yosys
/
tests
/
techmap
/
recursive.v
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2019-08-20 20:05:16 -07:00
module
top
;
sub
s0
();
foo
f0
();
endmodule
module
foo
;
sub
s0
();
endmodule
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