mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-05 11:35:20 +02:00
6 lines
64 B
Verilog
6 lines
64 B
Verilog
|
module a;
|
||
|
|
wire [5:0]x;
|
||
|
|
wire [3:0]y;
|
||
|
|
assign y = (4)55;
|
||
|
|
endmodule
|