mirror of https://github.com/YosysHQ/yosys.git
12 lines
132 B
Verilog
12 lines
132 B
Verilog
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module m;
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parameter PARAM = 0;
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endmodule
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(* foo="bar" *)
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module top;
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(* dont_touch *)
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wire w;
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m #(.PARAM(4)) inst();
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endmodule
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