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yosys/docs/source/code_examples/intro/counter_outputs.ys

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WIP merging synth phases with example Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`. Also updating the counter example to match. Aims to reduce redundancy, and simplify the getting started section. Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).
2023-12-07 01:04:46 +01:00
# read
presentation progress
2014-01-29 12:15:38 +01:00
read_verilog counter.v
hierarchy -check -top counter
Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
2023-08-02 23:20:29 +02:00
show -notitle -format dot -prefix counter_00
presentation progress
2014-01-29 12:15:38 +01:00
WIP merging synth phases with example Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`. Also updating the counter example to match. Aims to reduce redundancy, and simplify the getting started section. Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).
2023-12-07 01:04:46 +01:00
# elaborate
proc
show -notitle -format dot -prefix counter_proc
presentation progress
2014-01-29 12:15:38 +01:00
WIP merging synth phases with example Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`. Also updating the counter example to match. Aims to reduce redundancy, and simplify the getting started section. Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).
2023-12-07 01:04:46 +01:00
opt
Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
2023-08-02 23:20:29 +02:00
show -notitle -format dot -prefix counter_01
presentation progress
2014-01-29 12:15:38 +01:00
# mapping to internal cell library
Progress in presentation
2014-06-26 22:05:39 +02:00
techmap; opt
presentation progress
2014-01-29 12:15:38 +01:00
Progress in presentation
2014-06-26 22:05:39 +02:00
splitnets -ports;;
Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
2023-08-02 23:20:29 +02:00
show -notitle -format dot -prefix counter_02
presentation progress
2014-01-29 12:15:38 +01:00
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
2023-08-02 23:20:29 +02:00
show -notitle -lib mycells.v -format dot -prefix counter_03