yosys/docs/source/code_examples/intro/counter.ys

# read design
read_verilog counter.v
hierarchy -check -top counter

# the high-level stuff
proc; opt; memory; opt; fsm; opt

# mapping to internal cell library
techmap; opt

# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib

# mapping logic to mycells.lib
abc -liberty mycells.lib

# cleanup
clean

# write synthesized design
write_verilog synth.v
Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00			`# read design`
presentation progress 2014-01-29 12:15:38 +01:00			`read_verilog counter.v`
			`hierarchy -check -top counter`

			`# the high-level stuff`
			`proc; opt; memory; opt; fsm; opt`

			`# mapping to internal cell library`
Progress in presentation 2014-06-26 22:05:39 +02:00			`techmap; opt`
presentation progress 2014-01-29 12:15:38 +01:00
			`# mapping flip-flops to mycells.lib`
			`dfflibmap -liberty mycells.lib`

			`# mapping logic to mycells.lib`
			`abc -liberty mycells.lib`

			`# cleanup`
			`clean`

Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert. 2023-08-02 23:20:29 +02:00			`# write synthesized design`
			`write_verilog synth.v`