mirror of https://github.com/YosysHQ/yosys.git
10 lines
244 B
Plaintext
10 lines
244 B
Plaintext
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verific -sv <<EOF
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module top(input clk, input a, input b);
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prop_unsupported: assert property (@(posedge clk) a ##1 @(posedge b) ##1 a);
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endmodule;
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EOF
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logger -expect error "Mixed clocking is currently not supported" 1
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verific -import top
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