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yosys/tests/verific/mixed_flist.ys

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tests/verific: add mixed -f list case
2026-01-28 12:55:42 +01:00
verific -f -sv mixed_flist.flist
tests/verific: ensure mixed -f requires VHDL unit
2026-01-29 07:46:10 +01:00
verific -import sv_top
tests/verific: add mixed -f list case
2026-01-28 12:55:42 +01:00
select -assert-mod-count 1 sv_top