mirror of https://github.com/YosysHQ/yosys.git
15 lines
206 B
VHDL
15 lines
206 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity vhdl_mod is
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port (
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a : in std_logic;
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y : out std_logic
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);
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end entity vhdl_mod;
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architecture rtl of vhdl_mod is
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begin
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y <= a;
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end architecture rtl;
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