mirror of https://github.com/YosysHQ/yosys.git
15 lines
289 B
Plaintext
15 lines
289 B
Plaintext
|
read_verilog alu_sub.v
|
||
|
|
proc
|
||
|
|
hierarchy -auto-top
|
||
|
|
|
||
|
|
select -assert-mod-count 1 adder
|
||
|
|
select -assert-mod-count 1 wrapper
|
||
|
|
select -assert-mod-count 1 alu
|
||
|
|
|
||
|
|
sdc -keep_hierarchy alu_sub.sdc
|
||
|
|
flatten
|
||
|
|
|
||
|
|
select -assert-mod-count 0 adder
|
||
|
|
select -assert-mod-count 1 wrapper
|
||
|
|
select -assert-mod-count 1 alu
|