2019-10-18 12:33:35 +02:00
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read_verilog ../common/memory.v
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2019-08-23 00:50:45 +02:00
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hierarchy -top top
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proc
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memory -nomap
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equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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2019-08-28 21:30:35 +02:00
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sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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2019-08-23 00:50:45 +02:00
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design -load postopt
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2019-08-22 21:30:49 +02:00
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cd top
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2019-08-21 20:52:07 +02:00
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select -assert-count 1 t:SB_RAM40_4K
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2019-08-22 21:35:35 +02:00
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select -assert-none t:SB_RAM40_4K %% t:* %D
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