2019-08-21 20:52:07 +02:00
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read_verilog latches.v
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2019-08-28 21:21:15 +02:00
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design -save read
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proc
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async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
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flatten
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synth_ice40
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load read
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2019-08-20 06:50:05 +02:00
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synth_ice40
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2019-08-22 21:30:49 +02:00
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cd top
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select -assert-count 4 t:SB_LUT4
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select -assert-none t:SB_LUT4 %% t:* %D
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