mirror of https://github.com/YosysHQ/yosys.git
10 lines
266 B
Plaintext
10 lines
266 B
Plaintext
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read_liberty retention.lib
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rename retention_cell retention_cell_lib
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read_verilog retention.lib.verilogsim
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proc
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rename retention_cell retention_cell_vlog
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async2sync
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equiv_make retention_cell_lib retention_cell_vlog equiv
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equiv_induct equiv
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equiv_status -assert equiv
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