mirror of https://github.com/YosysHQ/yosys.git
12 lines
203 B
Plaintext
12 lines
203 B
Plaintext
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read_verilog << EOT
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module top(input clk, arst, d, output reg q);
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always @(posedge clk or posedge arst)
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if (arst) q <= 0;
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else q <= d;
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endmodule
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EOT
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proc
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async2sync
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dump w:\$auto\$async2sync*
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