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de6aa77dc835525cd56f64d0ebf9a2200eecb419
yosys
/
tests
/
errors
/
syntax_err11.v
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
module
a
;
parameter
integer
real
x
=
0
;
endmodule
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