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yosys/docs/source/code_examples/techmap/mymul_test.ys

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Progress in presentation
2014-02-16 17:56:19 +01:00
read_verilog mymul_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v \
-map mymul_map.v;;
rename test test_mapped
read_verilog mymul_test.v
miter -equiv test test_mapped miter
flatten miter
sat -verify -prove trigger 0 miter
splitnets -ports test_mapped/A
docs: moving code examples Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
2023-11-14 00:55:39 +01:00
show -prefix mymul -format dot -notitle test_mapped