docs/source/code_examples/techmap/mymul_test.ys

read_verilog mymul_test.v
hierarchy -check -top test

techmap -map sym_mul_map.v \
        -map mymul_map.v;;

rename test test_mapped
read_verilog mymul_test.v
miter -equiv test test_mapped miter
flatten miter

sat -verify -prove trigger 0 miter

splitnets -ports test_mapped/A
show -prefix mymul -format dot -notitle test_mapped
Progress in presentation 2014-02-16 17:56:19 +01:00			`read_verilog mymul_test.v`
			`hierarchy -check -top test`

			`techmap -map sym_mul_map.v \`
			`-map mymul_map.v;;`

			`rename test test_mapped`
			`read_verilog mymul_test.v`
			`miter -equiv test test_mapped miter`
			`flatten miter`

			`sat -verify -prove trigger 0 miter`

			`splitnets -ports test_mapped/A`
docs: moving code examples 2023-11-14 12:55:39 +13:00			`show -prefix mymul -format dot -notitle test_mapped`