yosys/tests/arch/analogdevices/mul_unsigned.ys

read_verilog mul_unsigned.v
hierarchy -top mul_unsigned
proc

equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module
select -assert-count 1 t:RBBDSP
select -assert-count 75 t:FFRE
select -assert-none t:RBBDSP t:FFRE %% t:* %D