mirror of https://github.com/YosysHQ/yosys.git
16 lines
289 B
Systemverilog
16 lines
289 B
Systemverilog
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module top (
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input logic clk,
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input logic idx,
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output logic [2:0] out_data
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);
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(* nomem2reg *)
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logic my_array [3:2][2:0] = '{'{0, 1, 1}, '{1, 0, 1}};
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always_comb begin
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for (int i=0; i < 3; i++) begin
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out_data[i] = my_array[{1'b1, idx}][i];
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end
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end
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endmodule
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