mirror of https://github.com/YosysHQ/yosys.git
7 lines
106 B
Verilog
7 lines
106 B
Verilog
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module add_multi_const(
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input [7:0] x,
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output [7:0] y
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);
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assign y = 8'd1 + 8'd2 + 8'd3 + x;
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endmodule
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