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Progress in presentation
2014-02-16 14:32:56 +01:00
read_verilog sym_mul_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v;;
docs: moving code examples
2023-11-14 12:55:39 +13:00
show -prefix sym_mul -format dot -notitle -lib sym_mul_cells.v
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