This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-08-31 18:24:48 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
9ce69521316d320c1078089f0b7cf63127950621
yosys
/
docs
/
source
/
code_examples
/
synth_flow
/
memory_01.ys
T
4 lines
71 B
Plaintext
Raw
Normal View
History
Unescape
Escape
presentation progress
2014-02-02 22:26:26 +01:00
read_verilog memory_01.v
hierarchy -check -top test
proc;; memory; opt
Reference in New Issue
Copy Permalink