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yosys/techlibs/quicklogic/Makefile.inc

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quicklogic: PolarPro 3 support Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-17 03:34:30 +01:00
OBJS += techlibs/quicklogic/synth_quicklogic.o
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-07-07 15:27:21 +02:00
$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v))
quicklogic: ABC9 synthesis
2021-04-12 11:33:40 +02:00
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-07-07 15:27:21 +02:00
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v))
$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v))