mirror of https://github.com/YosysHQ/yosys.git
13 lines
282 B
Plaintext
13 lines
282 B
Plaintext
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read_verilog -sv <<EOF
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module top( input[2:0] a );
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always_comb begin
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// example from 1800-2012 12.4.2
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unique if ((a==0) || (a==1)) $display("0 or 1");
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else begin
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unique if (a == 2) $display("2");
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else if (a == 4) $display("4");
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end
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end
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endmodule
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EOF
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