mirror of https://github.com/YosysHQ/yosys.git
9 lines
141 B
Plaintext
9 lines
141 B
Plaintext
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read_verilog fir_4tap.v
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hierarchy -auto-top
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proc; opt_clean
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equiv_opt -async2sync csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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