mirror of https://github.com/YosysHQ/yosys.git
8 lines
107 B
Verilog
8 lines
107 B
Verilog
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module add_with_const(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a + b + c + 8'd42;
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endmodule
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