mirror of https://github.com/YosysHQ/yosys.git
10 lines
179 B
Verilog
10 lines
179 B
Verilog
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module add_two_chains(
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input [7:0] a, b, c, d,
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input [7:0] e, f, g, h,
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output [7:0] y1,
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output [7:0] y2
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);
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assign y1 = a + b + c + d;
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assign y2 = e + f + g + h;
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endmodule
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