mirror of https://github.com/YosysHQ/yosys.git
7 lines
115 B
Verilog
7 lines
115 B
Verilog
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module add_signed(
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input signed [7:0] a, b, c, d,
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output signed [9:0] y
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);
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assign y = a + b + c + d;
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endmodule
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