mirror of https://github.com/YosysHQ/yosys.git
11 lines
155 B
Verilog
11 lines
155 B
Verilog
|
module add_mixed_widths(
|
||
|
|
input [7:0] a,
|
||
|
|
input [3:0] b,
|
||
|
|
input [15:0] c,
|
||
|
|
input [7:0] d,
|
||
|
|
output [15:0] y
|
||
|
|
);
|
||
|
|
assign y = a + b + c + d;
|
||
|
|
endmodule
|
||
|
|
|