mirror of https://github.com/YosysHQ/yosys.git
8 lines
166 B
Verilog
8 lines
166 B
Verilog
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module dffe_wide_11( input clk, input [1:0] en,
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input [3:0] d1, output reg [3:0] q1,
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);
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always @( posedge clk ) begin
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if ( en[0] )
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q1 <= d1;
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end
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endmodule
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