docs/source/code_examples/show/cmos.ys

# pitfall
read_verilog cmos.v
prep -top cmos_demo
techmap
abc -liberty ../intro/mycells.lib;;
show -format dot -prefix cmos_00

# reset
design -reset

# fixed output
read_verilog cmos.v
prep -top cmos_demo
techmap
splitnets -ports
abc -liberty ../intro/mycells.lib;;
show -lib ../intro/mycells.v -format dot -prefix cmos_01
docs: Tidying image generation 2023-11-15 17:39:37 +13:00			`# pitfall`
			`read_verilog cmos.v`
			`prep -top cmos_demo`
			`techmap`
Remove trailing whitespaces 2026-06-23 07:24:59 +02:00			`abc -liberty ../intro/mycells.lib;;`
docs: Tidying image generation 2023-11-15 17:39:37 +13:00			`show -format dot -prefix cmos_00`

			`# reset`
			`design -reset`

			`# fixed output`
			`read_verilog cmos.v`
			`prep -top cmos_demo`
			`techmap`
			`splitnets -ports`
Remove trailing whitespaces 2026-06-23 07:24:59 +02:00			`abc -liberty ../intro/mycells.lib;;`
docs: Tidying image generation 2023-11-15 17:39:37 +13:00			`show -lib ../intro/mycells.v -format dot -prefix cmos_01`