mirror of https://github.com/YosysHQ/yosys.git
32 lines
530 B
Plaintext
32 lines
530 B
Plaintext
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read_verilog << EOT
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module test();
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wire [31:0] in;
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wire [31:0] out;
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assign out = in + 16;
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endmodule
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EOT
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constmap -cell const_cell O value
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select -assert-count 1 t:const_cell
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select -assert-count 1 r:value=16
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design -reset
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read_verilog << EOT
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module test();
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wire [31:0] in;
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wire [31:0] out1;
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wire [31:0] out2;
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assign out1 = in + 16;
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assign out2 = in + 32;
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endmodule
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EOT
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constmap -cell const_cell O value
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select -assert-count 2 t:const_cell
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select -assert-count 1 r:value=16
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select -assert-count 1 r:value=32
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