mirror of https://github.com/YosysHQ/yosys.git
11 lines
161 B
Plaintext
11 lines
161 B
Plaintext
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read_verilog <<EOT
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module top(input i, j, s, output o, p);
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assign o = s ? j : i;
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assign p = ~i;
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endmodule
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EOT
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select t:$mux
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aigmap -select
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select -assert-any %
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